1. Field of the Invention
The present invention relates to testing of computer systems. More specifically, the present invention relates to a method and an apparatus for accelerated Soft Error Rate (SER) testing of circuitry, including integrated circuits and memory chips.
2. Related Art
As technology advances give rise to ever higher density memory chips and increasing system clock frequencies it is imperative to have the capability to follow design rules to ensure immunity to transient errors caused by bit flipping due to radioactive decay from parts-per-million level contaminants in chip packaging materials. Without the ability to generate, stimulate and observe these phenomena it is difficult or impossible to create rules for chip designers to use to adequately design systems that are immune to Soft Error Rate (SER) or signal integrity interrupts.
Currently, it is costly and dangerous to accelerate SER by exposing unpackaged or prepackaged chips to radioactive isotopes. Accelerating alpha and/or beta particles to induce SER events has heretofore required access to facilities that have isotopic sources that are licensed by the US. Nuclear. Regulatory. Commission plus state and local licensing organizations. This creates a substantial barrier for chip designing organizations to acquire their own radiation sources/facilities. Because of the combination of cost, complexity, and personnel safety issues, companies typically pay substantial fees for irradiation experiments in licensed government or private radiation facilities.
Hence, what is needed is a method for accelerated SER testing of circuitry that is low-cost and environmentally safe as compared to current testing methods.